Quick yield ramp-up is critical for IC manufacturing. During a yield ramp-up process, systematic yield limiters are usually identified using yield learning methods. As the circuit feature size continuously shrinks and the design complexity continuously increases, however, traditional yield learning methods such as inline inspection, memory bitmapping and test chips are becoming less effective. Statistical yield learning methods based on volume diagnosis have recently been developed. Diagnosis results for a large number of failing devices contain valuable defect information including types, locations, physical topology, and design features. With the employment of various statistical methods, systematic issues and/or dominant defect mechanisms may be extracted from these diagnosis results.
For practical applications, a yield learning method based on volume diagnosis should be able to use reasonable computational resources to process a large number of failing dies within a short period of time. While the performance of diagnosis algorithms have been improved by various techniques including pattern sampling, fault dictionary, and machine learning, diagnosing of large circuit designs still requires a large amount of memory.
Even though the number of processors in modern workstations has increased significantly, the amount of physical memory does not increase as fast. A conventional diagnosis tool may require up to hundreds of gigabytes of memory for a design with hundreds of millions of gates. For current workstations with the largest memory and tens of processors, the number of concurrently running diagnosis programs is still very limited because only a few diagnosis programs will use up all the memory. As a result, most of the processors will stay idle. The low efficiency of resource utilization, in addition to the increasing processor time for each failing die, presents a serious challenge to diagnosis throughput and thus to practical applications of the yield learning methods based on volume diagnosis.